Junction Field Effect Transistors (JFETs) and Metal Semiconductor Field Effect Transistors (MESFETs) are known in the art. JFETs and MESFETs are useful for high-speed applications, in low-power integrated circuits and in super computers. Very Large Scale Integrated (VLSI) MESFET circuits are used in information processing systems such as telecommunications systems, telemetry systems, and the like.
Typically, N channel prior art JFETs made from Silicon (Si) or Gallium Arsenide (GaAs) have: N.sup.+ source and drain regions; a PN semiconductor junction gate; a uniformly doped N type channel between the source and the drain regions; and a uniformly doped P type reversed biased substrate or a semi-insulating substrate. Prior art N channel MESFETs have identical regions, but a Schottky diode gate. FIG. 1A shows a representative three-dimensional cross sectional view of a prior art MESFET 50. The channel is normally off, preventing current flow. When a bias is applied to the gate 52, a depletion layer 54, which controls current flow, is modulated in the intrinsic channel (directly under the gate). Extrinsic channel 56, which separates the intrinsic channel from the device's source 58 and drain 60 is a source of channel resistance. MESFETs and JFETs require an extrinsic channel 56 to prevent drain 60 to gate 52 punchthrough and, to a lesser extent to prevent source 58 to gate 52 punchthrough. MESFET drive capability, output power, switching speed and gain are directly affected by both extrinsic and intrinsic channel resistance.
Since, when the intrinsic channel resistance is large enough, extrinsic channel resistance may be ignored, the traditional approach to improving integrated circuit performance, called "scaling," was to shrink intrinsic transistor and circuit features. Scaling reduces circuit loads and, for JFETs and MESFETs, device capacitances and channel lengths. For prior art MESFETs and JFETs, this scaling led to first order performance improvements.
However, while scaling provided performance improvements initially, eventually, the devices shrunk to the point that intrinsic channel delay was not the dominating performance parameter. Then, extrinsic channel resistance and carrier transit time (between device contacts), which had been overshadowed by intrinsic channel delays, became pronounced and limited performance improvement.
Besides channel resistance, MESFET performance is a function of the MESFET's threshold voltage (V.sub.t), and device capacitances. V.sub.t is determined by: EQU V.sub.t =V.sub.bi -V.sub.p,
where V.sub.bi is the built-in potential of the metal-semiconductor junction, and V.sub.p is the pinchoff voltage defined by: EQU V.sub.p =(q/.epsilon.).intg..sub.a.sup.o yN.sub.d dy
where q is the electronic charge, and .epsilon. is the dielectric constant. As the doping density N.sub.d, averaged over the entire area of the channel, is low, V.sub.p will be small, making V.sub.t less negative, needed for a good device. The junction capacitance (C.sub.j) is also low.
These and other disadvantages of prior art MESFETs are disclosed in detail in Chao et al., "Experimental Comparison in The Electrical Performance of Long and Ultrashort Gate-Length GaAs MESFETs," IEEE Electron Devices Letters, vol. EDL-3, pp. 187-190 (1982) and, in Chao et al., "Channel Length Effects in quarter-micrometer Gate-Length GaAs MESFETs," IEEE Electron Devices Letters, vol. EDL-4, pp. 326-328 (1982). Other disadvantages disclosed include short channel effect problems encountered in prior art MESFETs, such as, a less positive V.sub.t, a decrease of transconductance, and failure to reach saturation. For example, the high E field of a short channel device increases electron channel velocity in an N channel MESFET. However, without a sufficient reduction in extrinsic channel delay, an improvement in channel velocity is lost.
One prior art approach to reducing the short-channel effects is to increase the impurity (dopant) concentration in the channel. Most prior art Si or GaAs FETs have a uniform, lateral doping concentration, i.e., in the x and z direction. However, the dopant level N.sub.d has a Gaussian distribution as a function of depth (in the y direction). These prior art devices have a high transconductance near pinchoff, and have less device related noise. In one prior art variation, the channel doping has a single discontinuity at some point in the channel, but the dopant level still varies with depth on each side of the discontinuity. Increasing channel dopant decreases free carrier mobility and device pinchoff voltage (V.sub.p). Further increasing dopant concentration enhances leakage current and impairs device transconductance.
Another problem with prior art MESFETs occurs when a voltage V.sub.D is applied to the MESFET's drain. The channel voltage drop increases in the direction of the channel (x), from the source 58 (0V) to V.sub.D at the drain 60. Consequently, the gate contact 62 is increasingly reverse biased from the source to the drain and, the width of the depletion 54, also, increases in the same direction. The depletion region 54 is widest at the drain end of the intrinsic channel, x=x.sub.4. The depletion region 54 acts as an insulating region, constricting the channel opening for electron flow. This constriction is more severe for Si, which has lower mobility than GaAs mobility. Increasing channel doping to reduce this constriction decreases mobility, decreasing device transconductance and, the depletion region 54 decreases, increasing gate capacitance. Thus both DC and AC gain are reduced.
Typically, a broad-beam ion implantation technique is used to control the active channel doping in MESFET devices. Higher dose implants form source and drain regions with some separation from the gate. Broad beam ion implantation provides a dopant density N.sub.d (y) defined by: EQU N.sub.d (y)=N.sub.do exp(-Y.sup.2),
where:
Y=(y-y.sub.n)/y.sub.b ; PA1 N.sub.do is the peak of a doping profile; PA1 y.sub.n is the distance of the peak from the top surface; PA1 y.sub.b =.infin.2.sigma..sub.n ; PA1 .sigma..sub.n is the standard deviation (the straggle) of the implanted impurities; and PA1 y is the depth of the doping profile below the metal/silicon interface at the gate.
As the resulting dopant density does not vary in the x-direction, a non-uniform channel doping requires additional lithography and masking steps, increasing complexity and defects. These extra masking steps can be avoided by using a focussed ion beam technology as disclosed in Evanson et al., "Fabrication and performance of GaAs MESFETs with graded channel doping using focussed ion-beam implantation," IEEE Electron Devices Lett, vol. EDL-9pp. 281-283 (1988).